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MP2935 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 1 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. the future of analog ic technology description MP2935 is a high-efficiency, 4-phase, synchronous, buck-switching pwm controller with an svid interface for high-performance intel processors. the multi-phase pwm output signals can be configured for up to 4-phase operation with interleaved switching. MP2935 adopts three-logic-level pwm outputs for enhanced noise immunity and flexible fault management. depending on the power states set by svid command, the multi-phase channel can switch between multiphase and single- phase operation. in addition, MP2935 supports programmable load-line resistance. as a result, the output voltage is always optimally positioned for a load transient. the chip also provides accurate and reliable short-circuit protection with adjustable current limit threshold and a delayed vr_rdy output that is masked during on-the-fly output voltage changes to eliminate false triggering. MP2935 performance is specified over the junction temperature range of -10c to 125c. the chip is available in 40-lead qfn package. features ? vr12.5 compliant ? multi-phase operation at up to 2mhz per phase ? tri-state pwm outputs for driving mps intelli-phase tm devices ? power-saving modes maximize efficiency during light load and deeper-sleep operation ? active current balancing between output phases ? independent current limit and load line setting inputs for additional design flexibility ? 8-bit digitally programmable 0v to 3.04v output through serial vid interface ? overload and short-circuit protection with latch-off delay ? output current monitor ? fault latch output ? regulator temperature monitor ? available in a 6mmx6mm 40-lead qfn package applications ? power supplies for next-generation intel? processors all mps parts are lead-free, halogen free, and adhere to the rohs directive. for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 2 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical application circuit
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 3 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. ordering information part number* package top marking junction temperature (t j ) MP2935dqk 6x6mm qfn40 MP2935 -40c to +125c MP2935adqk 6x6mm qfn40 MP2935a -40c to +125c * for tape & reel, add suffix ?z (e.g. MP2935dqk?z). for rohs compliant packaging, add suffix ?lf (e.g. MP2935dqk?lf?z) package reference top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 33 32 31 otpd otpg sdio alert# sclk vrrdy v rhot# addr temp imon cs4 cs3 cs2 cs1 vcm iccmax slope ocpset aamb vclamp aam fset vboot fault# pwm4 pwm3 pwm2 pwm1 ccm tmax vdd vcc en iref gndsen vosen vdiff idroop fb comp gnd absolute maximum ratings (1) vcc ..............................................0.3v to +6.5v vdd ..................................................................... ?0.3v to +4.0v gndsen ....................................?0.3v to +0.3v slope ........................................?0.3v to +26v all other pins ....................?0.3v to (vcc+0.3v) continuous power dissipation (t a = +25c) (2) ................................................................... 3.9w junction temperature ...............................150c lead temperature ...................................260c storage temperature.............. ?65c to +150c recommended operating conditions (3) vcc ........................................................................... 4.5v to 5.5v operating junction temp........ ?40c to +125c thermal resistance (4) ja jc 6x6 qfn40............................ 32 .......8 c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 4 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical characteristics vcc = 5 v, gndsen = gnd, en = vcc, vid = 0.50 v to 3.04 v, current going into pin is positive. t a = -10c to +100c, unless otherwise noted. parameter symbol conditions min typ max units voltage error amplifier error amplifier output voltage range (5) v comp 0.75 4.6 v t a = 25c. no load, closed-loop, measured at vosen pin to gndsen pin. active mode range. vid=1.50v to 3.04v -0.5 +0.5 % no load, closed-loop, measured at vosen pin to gndsen pin. active mode range. vid=1.50v to 3.04v -1 +1 % t a = 25c. no load, closed-loop, measured at vosen pin to gndsen pin. active mode range. vid=1.00v to 1.50v -8 +8 mv no load, closed-loop, measured at vosen pin to gndsen pin. active mode range. vid=1.00v to 1.50v -15 +15 mv t a = 25c. no load, closed-loop, measured at vosen pin to gndsen pin. active mode range. vid=0.500v to 1.000v -10 +10 mv dc output accuracy v out no load, closed-loop, measured at vosen pin to gndsen pin. active mode range. vid=0.500v to 1.000v -15 +15 mv line regulation v fb v cc = 4.75 v to 5.25 v 0.3 % input bias current i fb ? 1 +1 a output source current i comp fb forced to (v vid ? 3%), no droop -3 ma output sink current i comp fb forced to (v vid + 3%), no droop +3 ma open loop gain (5) 80 db unity gain bandwidth (5) gbw (err) comp = fb 20 mhz slew rate (5) c comp = 10 pf 25 v/ s remote sense amplifier bandwidth (5) gbw (rsa) 20 mhz gndsen current i gndsen gndsen=0.3v 10 400 a vosen current i vosen vosen=1v 15 50 a oscillator fset voltage v fset r fset = 64.9k ? to gnd 0.9 1.0 1.1 v frequency setting f sw t a = 25c, r fset = 64.9k ? , 4-phase configuration 540 600 660 khz in normal mode 0 800 a slope input current range (5) i slp in shutdown, or in uvlo, slope = 12 v ? 1 +1 a
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 5 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical characteristics (continued) vcc = 5 v, gndsen = gnd, en = vcc, vid = 0.50 v to 3.04 v, current going into pin is positive. t a = -10c to +100c, unless otherwise noted. parameter symbol conditions min typ max units current-sense and overcurrent protrection current limit level i vcm_oc r ocpset =80.6k ? , sink current from vcm pin 1.27 ma i vcm = -400a -24 -25 -26 a droop current i drp i vcm = +400a 24 25 26 a current balance amplifier common mode range (5) v cs_cm 1.0 3.5 v input current i cs csx=4v 1 a masked off-time (5) t offmskd measured from pwm turn-off 350 ns system interface control inputs en en low threshold voltage vil (en) 0.4 v en high threshold voltage vih (en) 0.8 v en high threshold hysteresis voltage vih (en) 100 mv enable high leakage iih (en) en=1.1v 2 a enable delay t 3 vcc uvlo, vboot is not 0v, en high to vout ramping (see figure 13) 2 5 ms thermal throttling control v temp adc register 17h=64h (100c) 0.9 v vrhot# low output impedance i vrhot# = 20ma, t a =25 o c 8 10 ? vrhot# high leakage current -1 1 a imon output imon current i mon i vcm = +400a 24 25 26 a imon clamp voltage v imonmax imon = float, i vcm = 400 a 1.3 v imon adc register 15h=c8h 1 v imon adc register 15h=64h 0.5 v vrrdy comparator under-voltage threshold vdiff (uv) relative to nominal dac voltage ? 300 mv relative to nominal dac voltage 400 mv over voltage threshold vdiff (ov) absolute voltage 3.30 v output low voltage v vrrdy (l) i vrrdy (sink) = 4ma 60 250 mv output high leakage i vrrdy v vrrdy = 3.3v 1 a relative to gndsen, vdiff falling ? 300 mv reverse voltage detection threshold (5) v osen (rv) relative to gndsen, vdiff rising ? 100 mv
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 6 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical characteristics (continued) vcc = 5 v, gndsen = gnd, en = vcc, vid = 0.50 v to 3.04 v, current going into pin is positive. t a = -10c to +100c, unless otherwise noted. parameter symbol conditions min typ max units ccm output output low voltage v ol i sink = 400a 10 200 mv output high voltage v oh i source = 400a 4.8 5 v pwm outputs output low voltage vol (pwm) i pwm(sink) = 400a 10 200 mv output high voltage (5) voh (pwm) i pwm(source) = 400a 4.8 5 v pwm tri-state leakage pwm = 2.5v -1 1 a supply vcc uvlo threshold voltage vcc uvlo vcc is rising 4.1 4.45 v uvlo hysteresis 200 mv en=high. both svid bus and internal id bus are idle. no load condition. 4-phase configuration. pwms not switching. 8 16 ma supply current i vcc en = 0v 50 250 a vdd regulator vdd regulator output voltage vdd 3.2 v svid interface (sclk, sdio, alert#) (5) leakage current il pull-up voltage: 0v to 1.1v -10 10 a pin capacitance (5) c pin 5 pf buffer on resistance (5) r on 4 8 13 ? vr clock to data delay (5) 4 8.3 ns setup time (5) 7 ns hold time (5) 14 ns
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 7 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. electrical characteristics (continued) vcc = 5 v, gndsen = gnd, en = vcc, vid = 0.50 v to 3.04 v, current going into pin is positive. t a = -10c to +100c, unless otherwise noted. parameter symbol conditions min typ max units adc voltage range reads ff. 1.28 v adc resolution 5 mv adc sampling rate (5) 3000 hz dnl (5) 1 lsb conversion time (5) 30 s dac slew rate (MP2935) soft-start slew rate 2.5 mv/s setvid_slow slew rate 2.5 mv/s setvid_fast slew rate 10 mv/s dac slew rate (MP2935a) soft-start slew rate 5 mv/s setvid_slow slew rate 5 mv/s setvid_fast slew rate 20 mv/s dac dac resolution 8 bits lsb 10 mv dnl 1 lsb inl 1 lsb tolerance -1 1 mv 1/2/3/4 phase detection pwm sink current 100 a pwm detection threshold voltage 2 2.5 3.2 v phase detect timer (5) 50 s notes : 5) guaranteed by design or characteri zation data, not tested in production.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 8 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. pin definition pin # name i/o description 1 otpd i factory otp programming only. connect to vcc for normal operation. 2 otpg i factory otp programming only. connect to gnd for normal operation. 3 sdio i/o data signal between cpu and serial vid controller. 4 alert# o alert signal from vid controller to cpu. 5 sclk i source synchronous clock from cpu. 6 vrrdy o vr ready output. open drain output signal. 7 vrhot# o voltage regulator thermal throttling logic output. actively pulls low if temperature at the monitoring point connected to temp exceeds the programmed vrhot# temperature threshold. 8 addr i svid address setting pin. refer to table 6 for address assignment. 9 temp i/o analog temperature signal input. 10 imon o analog total load current signal. sources a current proportional to the sensed total load current. connect a resistor from imon to gnd to program the gain. 11 aam i advanced asynchronous mode (aam) timing control input. a resistor between this pin to ground sets the aam mode turn-on threshold voltage. 12 fset i multiphase frequency-setting input. a resistor connected between fset and gnd sets the oscillator frequency. the phase switching frequency will be divided by number of the operating phase. 13 vboot i/o v boot voltage set. refer to table 3 for vboot voltage assignment. 14 fault# o vr fault#. asserts low to notify the platform of a vr fault condition. 15 pwm4 o 16 pwm3 o 17 pwm2 o 18 pwm1 o tri-state logic-level pwm outputs. connecting the pwm2 and/or pwm3 and/or pwm4 outputs to vcc turns off that phase, allowing MP2935 to change the number of operating phases. the operating phase number is decided when the part is enable. the number of operating phase cannot be changed on-the-fly. 19 ccm o forced ccm operation enable. ccm st ays high in power states 00 and 01. actively pulls low when in power states 02 and 03 to enable dcm operation of the power stage. connec t it to the sync pin of intelli- phases tm . 20 tmax i max. temp. set. connect a resistor from tmax to gnd to set the maximum temperature. 21 cs4 i 22 cs3 i 23 cs2 i 24 cs1 i current balance inputs. measures the current level in each phase. float cs pins of unused phases. 25 vcm o buffered 2.5v reference. 26 iccmax i iccmax setting. set the pin voltage to program the desired iccmax level.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 9 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. pin definition (continued) pin # name i/o description 27 slope i pwm slope current input. connect a 100k ? resistor from vin (system?s 12v input voltage) to this pin to set the internal slope for pwm comparator. 28 ocpset i total current limit setting. 29 aamb i combine with aam pin, this pin sets the aam mode threshold voltage. 30 vclamp i connect a resistor to ground to set the per phase current limit. 31 comp i/o error amplifier output. 32 fb i inverting input of error amplifier. 33 idroop o droop current output. sources current that is proportional to the sensed output current. 34 vdiff o differential amplifier output. 35 vosen i remote core voltage sense input. connect to vccsense at microprocessor die. 36 gndsen i remote voltage sensing return. connect to ground at microprocessor die. 37 iref i internal bias cu rrent set. connect an 80.6k ? resistor from iref to gnd. 38 en i chip enable. 39 vcc i 5v supply voltage for the controller. need a 1 f capacitor for decoupling. 40 vdd o 3.3v ldo output for internal digital circuit only. need a 1 f capacitor for decoupling. do not connect to any other load. pad gnd i/o ground.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 10 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. typical performanc e characteristics performance waveforms are tested on the evaluation board of the design example section. v in = 12v, v cc = 5v, v out = 1.85v, i out = 0a, 600khz, unless otherwise noted. v out 1v/div. v r_rdy 500mv/div. v en 2v/div. v alert# 500mv/div. v r_rdy 1v/div. v en 5v/div. v out 1v/div. v pwm1 5v/div. v sw 10v/div. v pwm1 5v/div. v comp 100mv/div. v out /ac 20mv/div. v sw1 10v/div. v pwm1 5v/div. v comp 100mv/div. v out /ac 20mv/div. v pwm1 2v/div. v pwm2 2v/div. v pwm3 2v/div. v pwm4 2v/div. v diff 500mv/div. v pwm1 5v/div. v fault# 1v/div. v diff 500mv/div. v r_rdy 1v/div. v pwm4 5v/div. v fault# 1v/div. v osen 500mv/div. v fault# 1v/div. v diff 1v/div. v pwm1 5v/div. v osen 500mv/div. v fault# 2v/div. v r_rdy 1v/div. v pwm1 2v/div.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 11 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. functional block diagram current balance 1-/2-/3-/4- phase driver logic + - + - + - uvlo shutdown bias vr_hot# control + - + - reset reset reset set/ en 3.3v ldo pwm1 pwm2 pwm4 cs1 cs2 cs3 temp vrhot# gnd vdd vcc en fault vid+400mv vid-300mv + - vclamp aamb imon current sense iref fault ov uv oc bandgap aam fset slope + - -300mv rv vdiff 3.4v vosen oscillator pwm3 cs4 rvp ovp 2 ovp 1 uvp 1-ph + - reset fault clock divider idroop decay dcy ocpset + - + - gndsen vosen vdiff fb vid comp ccm mode control 1-ph e/a serial data link, registers, control 256 8-bits registers sclk sdio alert# vid 8-bits adc 8 8 vrset otpd 4 8 dac 8 -channel mux dvid vrrdy0 decay 4mhz id clock 24khz clock addr 4-bits adc 4 and otp imon temp vdiff (tbd) (tbd) (tbd) (tbd) (tbd) otpg fault fault# vr_ready monitor & delay, 2ms vrrdy vr settled comparator v fb vid +10 mv + - + - vrset fault dvid vrrdy0 vid-10mv decay - + 2.5v vcm tmax iccmax
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 12 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. operation MP2935 is a 4-phase vr12.5-compliant controller for intel microprocessors. it is a multiphase controller for up to 4-phase operation and is capable for multi-mode pwm/advanced asynchronous mode (aam) operation to maximize the efficiency over the load range. it includes blocks for a precision dac, remote voltage-sense amplifiers, an error amplifier, a ramp generator with input voltage feed-forward, a pwm comparator, aam control, load-line set, a vr-ready (vrrdy) monitor, a temperature monitor and serial vid (svid) registers. it also includes dynamic-phase current balancing and phase shedding. protection features include under-voltage lockout (uvlo), over-current protection (ocp), over-voltage protection (ovp), under-voltage protection (uvp) and reverse voltage protection (rvp). pwm operation MP2935 uses constant-switching?frequency current mode control and trailing-edge pwm operation with injected valley current signals. the pwm ramp of each phase combines with the sensed valley current to determine phase-current balance. figure 1 shows the operation principles. the phase clock turns the pwm on. when the combined ramp voltage hits v comp voltage the pwm turns off. the phase shift is applied between operating phases to minimize the input and output current ripple. in general, the controller needs to wait for the next clock during a load step transient to turn on the pwm to support the load current. the waiting time causes the extra output voltage to drop. to maximize the current support to reduce the output voltage drop during the transient load, MP2935 employs fast-pwm tm mode to respond immediately. during the load-step transient, the output voltage drop causes v comp to rise. when v comp rise fast enough to trigger the fast-pwm threshold, the controller overrides the phase clock and turns on all pwms without phase shifts. the pwm off of each phase is the same as for normal operation when the combined ramp hits v comp voltage. this fast-pwm mode maximizes the regulator?s di/dt slew rate to support the output load transient step and minimize the v out drop. when the power state is not ps0, the chip operates in single phase with aam mode to maximize the efficiency in light load condition. a detailed description of aam mode operation is described in ?aam control operation and diode emulation.? figure 1: block diagram of pwm operation
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 13 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. pwm operation and power states the user can select the total number of operating phases for MP2935, as described in ?switching frequency and the number of operating phases.? based on the power states, the actual operating phase dynamically switches between full phases or single phase to optimize the power conversion efficiency at heavy and light cpu loads. in ps0, MP2935 runs in full-phase pwm mode. while in light-load mode, ps1 to ps3, only phase 1 is in operation to maximize power conversion efficiency. during the dynamic vid transition issued by svid commands of either setvid_fast or setvid_slow, the power state changes to ps0 by default and runs in full-phase pwm mode. in addition to changing the number of phases, the operation mode can change dynamically. in ps0 mode, MP2935 runs in multiphase pwm mode with switching frequency controlled by the master clock. in other power states, MP2935 switches to aam mode where the switching frequency is no longer controlled by the master clock, but by the ripple voltage on the comp pin. thus, the switch frequency varies with the load current, resulting in maximum power conversion efficiency in low power states. in ps2 and ps3, diode emulation mode is enabled to maximize the efficiency at light load condition. the vr will switch back to aam mode if the over current alarm is clear before latch-off. table 1 summarizes the dynamically changes to phase number and operation modes based on the power state register set through svid commands. the power states are listed in order of power savings: ? ps0 represents full power or active mode ? ps1 is used in active mode or idle mode and represents a low current state, similar to psi# definition in vr11.1 or imvp6.5; it typically has a load < 20a. MP2935 runs in single phase (pwm1 only) aam/continuous current modulation (ccm) mode. ? ps2 is used in sleep mode and it represents a lower current state than ps1; it typically has a load < 5a. MP2935 runs in single phase (pwm1 only) aam with diode emulation enabled. ? ps3 (mode[1,0]= ?11?) is ultra-low current mode, lower than ps2; it typically has a load < 1a. MP2935 runs in single phase (pwm1 only) aam with diode emulation enabled. table 1: phase number and operation modes power state operating phases ccm pwm/aam 0 full phases 1 pwm 1 1 1 aam 2 1 0 aam 3 1 0 aam aam control operation and diode emulation with the exception of ps0, all other power states enable aam mode and run in single phase operation. figure 2 shows typical aam mode operation where switching frequency is no longer controlled by the master clock, but by the ripple voltage on the comp pin. pwm1 is set high when v comp reaches the aam threshold voltage which is set by two resistors, from aam pin to gnd and from aamb pin to gnd. out mon aamb common aam aam threshold voltage 15400 v ir v r ? ???? cs aamb 16 r r n ? ? out aam aam _ fraction 15400 v r v ? ? aam_fraction 6 out l _ pk pk cs 6 sw v v 0.5 i r 10 10 f3.42410 ? ? ? ? ?? ? ?? ?? v common is about 1v. v aam_fraction is part of the aam threshold voltage. n is the number of
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 14 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. active phase during ps0. i l_pk-pk is the peak to peak inductor current. out in out l_pk-pk in sw v(vv) i vlf ?? ? ?? whenever pwm is high, v ramp ramps up from 1v with a slew rate programmed by the current flowing into the slope pin. when v ramp reaches v comp , pwm resets to low. the ccm pin is tied to the sync pin of the intelli-phase tm . when the ccm pin is low, it enables diode emulation mode. in diode emulation mode the low side mosfet turns off once the inductor current reverses to keep the inductor current at 0a until the next pwm on pulse. in both ps0 and ps1, the ccm pin is high so the controller operates in ccm mode, which allows for negative inductor current. in ps2 and ps3, the ccm pin is low to enable diode emulation mode on the intelli-phase tm , allowing diode emulation mode operation. v ramp 1v pwm1 v comp aam threshold voltage ramp pwm1 q r s + - + - v comp aam threshold voltage figure 2: block diagram of aam operation and typical waveforms
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 15 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. switching frequency and the number of operating phases in normal operation in the ps0 power state, an external resistor connected from the fset pin to ground determines the clock frequency. to determine the switching frequency per phase, divide the clock by n, the number of phases, in use. if phase 4 is disabled by pulling up pwm4 to vcc, then divide the master clock by 3 for the frequency of the remaining phases. if both pwm3 and pwm4 are pulled up to vcc, then divide the master clock by 2 for the frequency of the remaining phases. if pwm2, pwm3 and pwm4 are pulled up to vcc, then the switching frequency of phase 1 equals the master clock frequency. if all phases are in use, then divide the master clock by 4. ?? 1.106 fset sw r 340000 f n ? ??? in single-phase aam mode, the switching frequency is almost constant, until it enters dcm mode then the frequency decrease proportionally with load current. current sensing and imon MP2935?s works seamlessly with the intelli- phase tm family to accurately sense output current to monitor the total output current to support adaptive voltage positioning (avp) and current limit detection. simply direct the total sensed phase current from all of the intelli- phases?s tm cs pins to vcm pin. when utilizing the intelli-phase?s tm accurate current sense output, it eliminates sensing error due to inductor dcr variation and removes design effort on dcr thermal compensation. this simple configuration is shown in figure 3. figure 3: intelli-phase tm current sensing circuit
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 16 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. the imon current is a current proportional to vcm pin current, vcm mon i i 16 ? . a resistor, r imon , from imon pin to gnd sets the gain from average sensed inductor current to imon voltage. a 1nf capacitor added in parallel with r imon filters the voltage ripple reflected from the inductor ripple current. imon 2048000 r iccmax ? if the desire iccmax is 100a, then select 20.5k ? for r imon . the voltage on the imon pin is clamped to prevent it from going above 1.3v. an 8-bit adc converts the imon voltage to the i out register. an imon voltage of 1.28v indicates the current has reached the value represented in the icc_max register. bottom bottom top r x x xiccmax r xiccmax vdd r 5 10 2 005 . 0 ) 005 . 0 ( ? ? ? ? set the iccmax register with a resistor divider from vdd voltage. vdd is a 3.3v output voltage from the controller. using a smaller resistance for r bottom will reduce variation. let?s say we choose r bottom to be 499 ? and the desired maximum current is 100a (iccmax=100a), then r top is calculated to be 2851 ? . to get the best possible accuracy, use two resistors to match the calculated resistance. phase current sensing MP2935 has individual inputs to monitor the current in each phase. the phase current information is combined with an internal ramp to create a current-balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. the current balance information is independent of the total inductor current information used for voltage positioning. the magnitude of the internal ramp can be programmed to optimize the transient response of the system. MP2935 also monitors the supply voltage to achieve feed-forward control whenever the supply voltage changes. a resistor connected from the power input voltage rail to slope pin determines the slope of the internal pwm ramp. in slope slope slope v 11 slope (v/s) 8 r 7000 c c4pf ?? ? ?? ? figure 4 shows the block diagram of the phase current sense and the ramp generator, and the idealized waveforms.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 17 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. v ramp pwm v comp clk inductor current 0v 0a l sw pwm intelliphase pwm vin vin gnd cs r vcm i csx csx pwm pwm comp. comp ramp vin r slope ++ MP2935 internal circuit c slope slope figure 4: block diagram of phase current sense and ramp generator
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 18 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. external resistors, r, from the csx pin to the vcm reference pin can convert the i cs current to a related voltage. to increase the current in any given phase, reduce the r for that phase. upon reaching the current limit, MP2935 switches to full phase pwm mode regardless of power state status to avoid inrush current stress to the phase 1 power stage. voltage regulation output voltage remote sensing is available. remote sensing allows the voltage regulator to compensate for various resistive drops in the power path and ensure that the voltage seen at the cpu die is the correct level independent of the load current. the vosen and gndsen pins connect to the kelvin sense leads at the die of the processor through the processor socket as the signals vcc_sense and vss_sense, respectively. this allows the voltage regulator to tightly control the processor voltage at the die, independent of layout inconsistencies and drops. this kelvin sense technique provides extremely tight load line regulation. treat these traces as noise-sensitive. for optimal load-line regulation performance, lay out the traces connecting these two pins to the kelvin sense leads of the processor in parallel and away from rapidly-rising voltage nodes (switching nodes) and other noisy traces. to achieve optimal performance, place common mode and differential mode rc filters to analog ground on vosen and gndsen. keep the filter resistors on the order of 10 ? so that they do not interact with the 50k ? input resistance of the differential amplifier. the voltage-mode control loop consists of a high- gain?bandwidth error amplifier. the 8-bit vid dac sets the non-inverting input voltage. the vid codes are listed in table 2. the output of the error amplifier goes to the comp pin, which sets the termination voltage for the internal pwm ramps. the inverting input, fb, connects to the output of the remote sense amplifier through a resistor, r fb , to sense and control the output voltage at the remote sense point. r fb generates the droop voltage as a function of the load current?commonly known as active voltage positioning ?by injecting the droop current, i drp , into the fb pin. the main loop compensation is incorporated into the feedback network connected between the fb and comp pins.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 19 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. table 2: svid code table dec vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v out 0 0 000 000 0 00 off 1 0 000 000 1 01 0.500 2 0 000 001 0 02 0.510 3 0 000 001 1 03 0.520 4 0 000 010 0 04 0.530 5 0 000 010 1 05 0.540 6 0 000 011 0 06 0.550 7 0 000 011 1 07 0.560 8 0 000 100 0 08 0.570 9 0 000 100 1 09 0.580 10 0 000 101 0 0a 0.590 11 0 000 101 1 0b 0.600 12 0 000 110 0 0c 0.610 13 0 000 110 1 0d 0.620 14 0 000 111 0 0e 0.630 15 0 000 111 1 0f 0.640 16 0 001 000 0 10 0.650 17 0 001 000 1 11 0.660 18 0 001 001 0 12 0.670 19 0 001 001 1 13 0.680 20 0 001 010 0 14 0.690 21 0 001 010 1 15 0.700 22 0 001 011 0 16 0.710 23 0 001 011 1 17 0.720 24 0 001 100 0 18 0.730 25 0 001 100 1 19 0.740 26 0 001 101 0 1a 0.750 27 0 001 101 1 1b 0.760 28 0 001 110 0 1c 0.770 29 0 001 110 1 1d 0.780 30 0 001 111 0 1e 0.790 31 0 001 111 1 1f 0.800 32 0 010 000 0 20 0.810 33 0 010 000 1 21 0.820 34 0 010 001 0 22 0.830 35 0 010 001 1 23 0.840 36 0 010 010 0 24 0.850 37 0 010 010 1 25 0.860 38 0 010 011 0 26 0.870 39 0 010 011 1 27 0.880 40 0 010 100 0 28 0.890 41 0 010 100 1 29 0.900 42 0 010 101 0 2a 0.910 43 0 010 101 1 2b 0.920 44 0 010 110 0 2c 0.930 45 0 010 110 1 2d 0.940 46 0 010 111 0 2e 0.950 47 0 010 111 1 2f 0.960 48 0 011 000 0 30 0.970
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 20 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. dec vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v out 49 0 0 1 1 0 0 01 31 0.980 50 0 0 1 1 0 0 10 32 0.990 51 0 0 1 1 0 0 11 33 1.000 52 0 0 1 1 0 1 00 34 1.010 53 0 0 1 1 0 1 01 35 1.020 54 0 0 1 1 0 1 10 36 1.030 55 0 0 1 1 0 1 11 37 1.040 56 0 0 1 1 1 0 00 38 1.050 57 0 0 1 1 1 0 01 39 1.060 58 0 0 1 1 1 0 10 3a 1.070 59 0 0 1 1 1 0 11 3b 1.080 60 0 0 1 1 1 1 00 3c 1.090 61 0 0 1 1 1 1 01 3d 1.100 62 0 0 1 1 1 1 10 3e 1.110 63 0 0 1 1 1 1 11 3f 1.120 64 0 1 0 0 0 0 00 40 1.130 65 0 1 0 0 0 0 01 41 1.140 66 0 1 0 0 0 0 10 42 1.150 67 0 1 0 0 0 0 11 43 1.160 68 0 1 0 0 0 1 00 44 1.170 69 0 1 0 0 0 1 01 45 1.180 70 0 1 0 0 0 1 10 46 1.190 71 0 1 0 0 0 1 11 47 1.200 72 0 1 0 0 1 0 00 48 1.210 73 0 1 0 0 1 0 01 49 1.220 74 0 1 0 0 1 0 10 4a 1.230 75 0 1 0 0 1 0 11 4b 1.240 76 0 1 0 0 1 1 00 4c 1.250 77 0 1 0 0 1 1 01 4d 1.260 78 0 1 0 0 1 1 10 4e 1.270 79 0 1 0 0 1 1 11 4f 1.280 80 0 1 0 1 0 0 00 50 1.290 81 0 1 0 1 0 0 01 51 1.300 82 0 1 0 1 0 0 10 52 1.310 83 0 1 0 1 0 0 11 53 1.320 84 0 1 0 1 0 1 00 54 1.330 85 0 1 0 1 0 1 01 55 1.340 86 0 1 0 1 0 1 10 56 1.350 87 0 1 0 1 0 1 11 57 1.360 88 0 1 0 1 1 0 00 58 1.370 89 0 1 0 1 1 0 01 59 1.380 90 0 1 0 1 1 0 10 5a 1.390 91 0 1 0 1 1 0 11 5b 1.400 92 0 1 0 1 1 1 00 5c 1.410 93 0 1 0 1 1 1 01 5d 1.420 94 0 1 0 1 1 1 10 5e 1.430 95 0 1 0 1 1 1 11 5f 1.440 96 0 1 1 0 0 0 00 60 1.450
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 21 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. dec vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v out 97 0 1 1 0 0 0 01 61 1.460 98 0 1 1 0 0 0 10 62 1.470 99 0 1 1 0 0 0 11 63 1.480 100 0 1 1 0 0 1 00 64 1.490 101 0 1 1 0 0 1 01 65 1.500 102 0 1 1 0 0 1 10 66 1.510 103 0 1 1 0 0 1 11 67 1.520 104 0 1 1 0 1 0 00 68 1.530 105 0 1 1 0 1 0 01 69 1.540 106 0 1 1 0 1 0 10 6a 1.550 107 0 1 1 0 1 0 11 6b 1.560 108 0 1 1 0 1 1 00 6c 1.570 109 0 1 1 0 1 1 01 6d 1.580 110 0 1 1 0 1 1 10 6e 1.590 111 0 1 1 0 1 1 11 6f 1.600 112 0 1 1 1 0 0 00 70 1.610 113 0 1 1 1 0 0 01 71 1.620 114 0 1 1 1 0 0 10 72 1.630 115 0 1 1 1 0 0 11 73 1.640 116 0 1 1 1 0 1 00 74 1.650 117 0 1 1 1 0 1 01 75 1.660 118 0 1 1 1 0 1 10 76 1.670 119 0 1 1 1 0 1 11 77 1.680 120 0 1 1 1 1 0 00 78 1.690 121 0 1 1 1 1 0 01 79 1.700 122 0 1 1 1 1 0 10 7a 1.710 123 0 1 1 1 1 0 11 7b 1.720 124 0 1 1 1 1 1 00 7c 1.730 125 0 1 1 1 1 1 01 7d 1.740 126 0 1 1 1 1 1 10 7e 1.750 127 0 1 1 1 1 1 11 7f 1.760 128 1 0 0 0 0 0 00 80 1.770 129 1 0 0 0 0 0 01 81 1.780 130 1 0 0 0 0 0 10 82 1.790 131 1 0 0 0 0 0 11 83 1.800 132 1 0 0 0 0 1 00 84 1.810 133 1 0 0 0 0 1 01 85 1.820 134 1 0 0 0 0 1 10 86 1.830 135 1 0 0 0 0 1 11 87 1.840 136 1 0 0 0 1 0 00 88 1.850 137 1 0 0 0 1 0 01 89 1.860 138 1 0 0 0 1 0 10 8a 1.870 139 1 0 0 0 1 0 11 8b 1.880 140 1 0 0 0 1 1 00 8c 1.890 141 1 0 0 0 1 1 01 8d 1.900 142 1 0 0 0 1 1 10 8e 1.910 143 1 0 0 0 1 1 11 8f 1.920 144 1 0 0 1 0 0 00 90 1.930
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 22 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. dec vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v out 145 10 0 1 0 00 191 1.940 146 10 0 1 0 01 092 1.950 147 10 0 1 0 01 193 1.960 148 10 0 1 0 10 094 1.970 149 10 0 1 0 10 195 1.980 150 10 0 1 0 11 096 1.990 151 10 0 1 0 11 197 2.000 152 10 0 1 1 00 098 2.010 153 10 0 1 1 00 199 2.020 154 10 0 1 1 01 0 9a 2.030 155 10 0 1 1 01 1 9b 2.040 156 10 0 1 1 10 09c 2.050 157 10 0 1 1 10 19d 2.060 158 10 0 1 1 11 0 9e 2.070 159 10 0 1 1 11 19f 2.080 160 10 1 0 0 00 0 a 0 2.090 161 10 1 0 0 00 1 a 1 2.100 162 10 1 0 0 01 0 a 22.110 163 10 1 0 0 01 1 a 3 2.120 164 10 1 0 0 10 0 a 4 2.130 165 10 1 0 0 10 1 a 5 2.140 166 10 1 0 0 11 0 a 6 2.150 167 10 1 0 0 11 1 a 7 2.160 168 10 1 0 1 00 0 a 8 2.170 169 10 1 0 1 00 1 a 9 2.180 170 10 1 0 1 01 0 a a 2.190 171 10 1 0 1 01 1 a b 2.200 172 10 1 0 1 10 0 a c 2.210 173 10 1 0 1 10 1 a d 2.220 174 10 1 0 1 11 0 a e 2.230 175 10 1 0 1 11 1 a f 2.240 176 10 1 1 0 00 0 b0 2.250 177 10 1 1 0 00 1 b1 2.260 178 10 1 1 0 01 0 b2 2.270 179 10 1 1 0 01 1 b3 2.280 180 10 1 1 0 10 0 b4 2.290 181 10 1 1 0 10 1 b5 2.300 182 10 1 1 0 11 0 b6 2.310 183 10 1 1 0 11 1 b7 2.320 184 10 1 1 1 00 0 b8 2.330 185 10 1 1 1 00 1 b9 2.340 186 10 1 1 1 01 0 ba 2.350 187 10 1 1 1 01 1 bb 2.360 188 10 1 1 1 10 0 bc 2.370 189 10 1 1 1 10 1 bd 2.380 190 10 1 1 1 11 0 be 2.390 191 10 1 1 1 11 1 bf 2.400 192 11 0 0 0 00 0c0 2.410
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 23 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. dec vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v out 193 1 1 0 000 0 1 c1 2.420 194 1 1 0 000 1 0 c2 2.430 195 1 1 0 000 1 1 c3 2.440 196 1 1 0 001 0 0 c4 2.450 197 1 1 0 001 0 1 c5 2.460 198 1 1 0 001 1 0 c6 2.470 199 1 1 0 001 1 1 c7 2.480 200 1 1 0 010 0 0 c8 2.490 201 1 1 0 010 0 1 c9 2.500 202 1 1 0 010 1 0 ca 2.510 203 1 1 0 010 1 1 cb 2.520 204 1 1 0 011 0 0 cc 2.530 205 1 1 0 011 0 1 cd 2.540 206 1 1 0 011 1 0 ce 2.550 207 1 1 0 011 1 1 cf 2.560 208 1 1 0 100 0 0 d0 2.570 209 1 1 0 100 0 1 d1 2.580 210 1 1 0 100 1 0 d2 2.590 211 1 1 0 100 1 1 d3 2.600 212 1 1 0 101 0 0 d4 2.610 213 1 1 0 101 0 1 d5 2.620 214 1 1 0 101 1 0 d6 2.630 215 1 1 0 101 1 1 d7 2.640 216 1 1 0 110 0 0 d8 2.650 217 1 1 0 110 0 1 d9 2.660 218 1 1 0 110 1 0 da 2.670 219 1 1 0 110 1 1 db 2.680 220 1 1 0 111 0 0 dc 2.690 221 1 1 0 111 0 1 dd 2.700 222 1 1 0 111 1 0 de 2.710 223 1 1 0 111 1 1 df 2.720 224 1 1 1 000 0 0 e0 2.730 225 1 1 1 000 0 1 e1 2.740 226 1 1 1 000 1 0 e2 2.750 227 1 1 1 000 1 1 e3 2.760 228 1 1 1 001 0 0 e4 2.770 229 1 1 1 001 0 1 e5 2.780 230 1 1 1 001 1 0 e6 2.790 231 1 1 1 001 1 1 e7 2.800 232 1 1 1 010 0 0 e8 2.810 233 1 1 1 010 0 1 e9 2.820 234 1 1 1 010 1 0 ea 2.830 235 1 1 1 010 1 1 eb 2.840 236 1 1 1 011 0 0 ec 2.850 237 1 1 1 011 0 1 ed 2.860 238 1 1 1 011 1 0 ee 2.870 239 1 1 1 011 1 1 ef 2.880 240 1 1 1 100 0 0 f0 2.890
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 24 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. dec vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v out 241 111 1 0 0 0 1 f1 2.900 242 111 1 0 0 1 0 f2 2.910 243 111 1 0 0 1 1 f3 2.920 244 111 1 0 1 0 0 f4 2.930 245 111 1 0 1 0 1 f5 2.940 246 111 1 0 1 1 0 f6 2.950 247 111 1 0 1 1 1 f7 2.960 248 111 1 1 0 0 0 f8 2.970 249 111 1 1 0 0 1 f9 2.980 250 111 1 1 0 1 0 fa 2.990 251 111 1 1 0 1 1 fb 3.000 252 111 1 1 1 0 0 fc 3.010 253 111 1 1 1 0 1 fd 3.020 254 111 1 1 1 1 0 fe 3.030 255 111 1 1 1 1 1 ff 3.040 load-line regulation the droop, known as adaptive voltage positioning (avp), on MP2935 can be generated by injecting the i drp current to the feedback resistor. the current output on the idroop pin is 16 1 of the i vcm current, which is proportional to the total output current. selecting the proper r fb1 value can achieve the desired load-line. in the case of zero droop, floats the idroop pin. figure 5 shows the block diagram of droop generation. 5 fb1 r1610droop ?? ? for 1m ? droop, r fb1 =1.6k ? . 1:16 vcm figure 5: block diagram of droop generator
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 25 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. output voltage offset programming after receiving the svid command for setting the offset (33h), the svid controller compares the vid plus the proposed offset with the maximum vid of ffh (3.04v), and rejects the svid command if this value exceeds ffh. if the vid plus proposed offset is less than ffh, the svid updates the register 33h and the dac ramps up/down to the new value of vid+offset with slow slew rate defined in register 25h. during ramp up/down to the new dac value, the svid rejects all svid commands, which is the same behavior as setvid_fast/slow. dynamic vid the svid bus sends out new target voltage and slew rate commands to the pwm ic. the vr responds by slewing to the new voltage in a controlled manner without falsely tripping vrrdy, over-voltage, or over-cu rrent protection circuits. to meet all market segment requirements, there are three different slew rates: fast, slow, and decay. during fast and slow vid transitions, the svid controller ramps up/down the vid code step-by-step. there is a 4mhz id clock for vid change, with defined vid step of 10mv, the maximum slew rate is up to 20mv/ s. during vid decay, the vr output voltage converges to the new vid target, but does not control the slew rate; the output voltage decays at a rate proportional to the load current. the vid change triggers a vr_rdy masking timer to prevent a vr_rdy failure. each vid change resets and restarts the internal vr_rdy masking timer. during the vid transition except vid decay, MP2935 forces a full-phase pwm operation and reset the power state to ps0 by default. setvid_fast/slow if the vr is in a low-power state and receives a new setvid_fast/slow command, then the vr exits the low-power state to normal mode (ps0), operating in full-phase pwm mode to move the voltage by the preset slew rate. the vr remains in ps0, until it receives a new power state command. setvid_decay in the case of a setvid_decay command, the vr automatically goes to ps2 or remain at ps3. setvid_decay command steps up the vid dac to the target vid at 10mv/step, with each step triggered by vr_settle assert. in the event of a setps command during the v out decay, MP2935 will enter into the requested power state after v out reaches the requested vid value. whenever the vr exits decay mode whenever it receives a setvid_fast/slow, enters ps0 power state, and ramps up/down to the new vid from its current vid. figure 6 shows the detailed diagram of the operation modes with the vid transition taken into consideration. figure 7(a) to 7(d) show the detailed signals of decay mode operation for different cases.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 26 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. vid dvid svid bus pwm1 pwm2 pwm3 mode0 mode1 0 0 1 0 ccm 0 0 1 0 0 1 setps_ (01h) s e tp s_ a( 0 1 h ) pkt setvid_ slow setvid_ decay setvid_d ecaya setps_a (11h) pkt setvid_sl owa setps_a(01h) pkt setps_ (01h) setps_ (11h) 1 1 power state change ps0 4phase pwm ccm vid(fast/slow) transient power state change vid decay power state change ps1 1phase aam ccm ps0 4phase pwm ccm ps1 1phase aam ccm ps2 1phase aam dcm ps3 1phase aam dcm note1: if vr is in a low power state and receive a setvid_fast/slow (up or down), then the vr exits the low power state to normal mode and set the ps register to 00h note3: with setvid_decay command, the vr automatically enters into ps2 mode. note2: the vr remain in ps0 until the cpu commands it to re-enter to a low power state. if vr is still slewing from previous setvid_fast/ slow command, the vr should reject the setps command. vout vr_settle note4: if vr is slewing down with a setvid_decay command and the next command is a setps , then vr could enter that power state with the decay rate. note 5: during decay mode, the vid is changed step by step following the vr _set signal. figure 6: detailed diagram of the operation modes
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 27 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. figure 7(a) figure 7(b)
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 28 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. figure 7(c) vid dvid/ !final_vid mode1 decay vr_settle vcore 1.2v 1.4v decay_settle alert# 250ns (min) 1.8v 1.4v 0.8v slow slew-rate dv<15mv decay changes 1 clk later than dvid 1.0v setvid_decay (1.0v) setps_0 case 4. cpu commands vid 1.8v decay to 1.0v. before vout reaches 1.0v target, set the power stage to ps0, setps(0) command. figure 7(d) figure 7: detail signal during decay mode operation
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 29 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. enable and disable to enable MP2935, the vcc supply voltage must exceed the uvlo upper threshold and the en pin must exceed its logic-high threshold. after start-up, vdd (3.3v) supplies the svid controller and interface. whenever the vcc voltage is less than the uvlo threshold or the en pin is logic low, MP2935 shuts down, and the controller sets all pwm outputs to a high-impedance (hi-z) state. soft-start and start-up into pre-biased output after enabling MP2935, the vr can start-up. the dac ramps up to the v boot voltage with the slew rate set in sr_slow register. during soft-start, the pwm is in hi-z state until the dac reaches fb voltage preventing the pre-biased output from discharging. upon completion of soft-start, vr_rdy asserts if there are no faults during a typical 2ms delay. set vboot voltage by using two resistors to form a resistor divider from vdd to set the vboot pin voltage. vdd pin is the internal 3.3v ldo output. table 3 shows the resistor pairs for different vboot voltages. table 3: v boot setting resistance v boot voltage r vboot_gnd r vdd_vboot 1.85v 768 ? 47.5k ? 1.8v 768 ? 19.6k ? 1.75v 768 ? 12.1k ? 1.7v 768 ? 8.45k ? 1.65v 768 ? 6.34k ? 1.6v 768 ? 5.11k ? 1.5v 768 ? 4.22k ? 1.35v 768 ? 3.48k ? 1.25v 768 ? 3.01k ? 1.2v 768 ? 2.55k ? 1.1v 768 ? 2.21k ? 1v 768 ? 2k ? 0.9v 768 ? 1.78k ? 0v 768 ? 1.58k ? 0.6v 768 ? 1.43k ? 0.8v 768 ? 1.27k ? vr_settle monitoring vr_settle signal indicates whether the dynamic vid (dvid) transition has completed. vr_settle is de-asserted when the vr controller receives a new vid code different from the previous one; vr_settle is asserted again when the output voltage is within 10 mv or one vid step of the target voltage. the falling edge of dvid indicates that the vid ramping will complete soon. when the svid controller receives a new vid target from the svid master, it asserts the dvid signal; then the svid controller ramps up/down the vid code step-wise to the target vid. the svid controller de-asserts dvid when the current vid code is within 10mv or one vid step of targeted voltage. then the sensed output voltage is compared to the dac output to determine vrsettle signal when the dvid is asserted. once dvid is asserted, it lasts for at least 250ns. the only condition that asserts and de-asserts vr_settle is the vid transition. vrsettle remains unchanged even if the output voltage exits the 10mv window when operating under a stable vid code. when the vid change is within 1 step, the svid controller de-asserts the dvid signal for a minimum of 500ns and vrsettle resets. vr_settle sets if the output is within 10mv after dvid is asserted. the svid responds with alert# after the ack signal from the cpu if vr_settle is asserted. fault monitoring and protections the fault monitoring and protections provided by MP2935 are listed below. 1) vr_rdy signals 2) under-voltage monitor and protection 3) over-voltage monitor and protection 4) reverse-voltage monitor and protection 5) over-current monitor and protection 6) thermal monitors and over-temperature indicator (vr_hot#, active low) 7) fault# (active low) signal
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 30 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. vr_rdy signal vrrdy pin is an active-high (open drain) output that indicates that the start-up sequence has completed and that the output voltage has moved to the v boot value or the svid programmed vid value. this signal is part of the start-up sequence for other voltage regulators, the clock, microprocessor reset, etc. vrrdy comparator monitors the operation of vr through the fault latch logic. the signal remains asserted during normal operation and de-asserts whenever a fault (ocp, ovp, etc.) or shutdown conditions occurred. this signal does not represent dc output accuracy through its vid value and does not track vid during dynamic vid events. vrrdy indicates that the vr is operating properly, not falsely trigger during dynamic vid transitions. vrready_0v flat is under register 34h configures multiple slaves (vrs) on the same bus on the server platforms. it is also used in notebook and desktop systems to program vrrdy operation when the vid command is set to 0v or off condition. if ?vr_rdy_0v? =0 (default, normal mode), then vr_rdy de-asserts if the vr is given a setvid (0.0v) command, i.e., the vr is off. if ?vr_rdy_0v?=1, then vrrdy does not de- assert when a setvid (0.0v) command is issued. this means that the 0v output is a valid voltage setting and the vr is ready to accept the next command. under this definition, vr_rdy only de-asserts at power-down or under fault conditions. see figure 8 for more details. figure 8: vr_rdy_0v operation waveforms
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 31 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. under-voltage detection under-voltage protection is independent of the over-current limit. a fault triggers if the output voltage is less than the vid value by 300mv or more for at least 1ms. then the vr shuts off and latches and vr_rdy goes low. note that most practical voltage regulators will trigger over- current before dropping below the -300mv under- voltage limit. refer to figure 9. figure 9: under-voltage protection over-voltage protection ovp circuit monitors the output for an over- voltage condition. there are two levels of over-voltage protection: ovp1 is the first level of over-voltage protection, and is defined as vid+400mv; ovp 2 is set at 3.40v. once the output voltage exceeds either of these two ovp levels, an over-voltage (ov) fault will trigger immediately. the first level ov detector (vid+400mv) is blanked until the first falling edge of the dvid signal after the part is enabled. this prevents the false latch with start-up with pre-biased output voltage. ovp1 monitor is also disabled during the vid decay transition. it re-activates after finishing vr_settle re-assertion transition. during fast or slow vid transitions, the ovp1 is blanked for 100 s. figure 10 summarizes the blanking conditions for the ovp1 monitor. the ovp2 monitor is active at all times when the controller is enabled regardless of fault conditions. this ensures that the load is protected against high-side mosfet leakage while the mosfets turn off. in the event of an ovp condition, the pwms are latched low with ccm=1 to turn off the high-side mosfets and turn on low-side mosfets to crowbar the output, while vrrdy de-asserts. the ovp latch can only reset when toggled enable, toggles the vcc, or when reverse- voltage protection (rvp) occurs. figure 10 shows the ovp fault latch for the two levels.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 32 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. figure 10: ovp protection blanking conditions
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 33 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. figure 11: ovp and rvp fault protection
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 34 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. reverse-voltage detection very large reverse inductor currents cause negative output voltages that harm the cpu and other output components. MP2935 provides rvp without additional system cost. the vosen pin monitors the output voltage: any time the vosen pin voltage falls below -300 mv, MP2935 triggers rvp by latching all pwm outputs to a high-z state. the reverse inductor current can quickly reset to 0a by dissipating the energy in the inductor through the input dc voltage source through the forward-biased body diode of the high-side mosfets. occasionally, ovp results in negative output voltage because turning on all low-side mosfets leads to very large reverse inductor current. the vr controller?s rvp monitoring function remains active even after ovp latch-off to prevent damage to the load by negative voltage. the rvp latch can only be reset by toggling enable, power cycling the vcc or when ovp occurs. see figure 11. over-current protection MP2935 uses vcm current, i vcm , to detect an over-current condition. vcm current is continually compared to an internal reference current. i vcm is provided by intelli-phase?s tm cs pin, see ?current sensing and imon? section for details. in n-phase configuration?where all phases are switching?the current limit occurs when the vcm current exceeds the oc threshold. the threshold is programmable via a resistor from ocpset pin to ground. for most designs, select oc threshold about 130% of the rated current. in power states psn (where n = 1 through 3) running in single phase mode, the oc threshold is divided by n, i.e. 1/n. n is the number of operating phases for power state 0 (ps0). see table 4. table 4: ocp level during ps1/2/3 over current trip level n=4 n=3 n=2 ps0 i oc i oc i oc ps1/2/3 i oc /4 i oc /3 i oc /2 whenever vcm current exceeds the oc threshold, an internal current limit amplifier controls the internal comp voltage cycle-by- cycle to turn off the pwm to maintain peak current below the oc limit level. if an oc event occurs for 1ms, an oc fault triggers and MP2935 shuts down with all pwm latched to high-z output, as shown in figure 12. the latch-off can only reset by either toggling vcc or toggling the en pin. program the oc level with the following equation: 7 ocpset oc 1.024 10 r i ? ? MP2935 also has a per-phase current limit to limit each phase?s duty cycle, so that each phase will not exceed a current level set by the user. this per-phase current limit can be programmed by setting a resistor from vclamp pin to ground. comp _ peak vclamp vclamp v r i ? 6 6 comp_peak cs per _ phase _ limit l _ pk pk out sw v r (i i ) 10 10 v 1 f 3.424 10 10 ? ? ? ? ????? ? ??? pwm vr_rdy vout iout i lim ccm 1ms figure 12: ocp fault protection
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 35 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. table 5: summary of fault protection fault fault duration prior to protection protection action comment general over-current 1ms an internal current limit amplifier controls the internal comp voltage, turning off the pwm and monitors for oc events cycle-by-cycle to keep the current below the oc limit level. all pwms are latched to high-z output if oc occurs continuously for 1ms. always on over-voltage of 3.4v immediate pwms ar e latched low and ccm is high. always on over-voltage of vid+ 400mv immediate pwms are latched low and ccm is high. disabled during vid transition and during soft start. under-voltage 1ms all pwms are latched to high-z output when uv occurs for at least 1ms. always on reverse voltage immediate all pwms ar e latched to high-z output. always on over-temperature immediate vr_hot# goes low. always on
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 36 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. monitoring (vr_hot#) and temperature zone MP2935 provides a temperature sense pin temp and vr_hot# signal to indicate an over- temperature event. vr_hot# can be routed to various system thermal management controllers. vrhot# pin is an open-drain output, active low and can be used to drive the cpu?s force thermal throttle input. the adc converts the v temp voltage to update the temperature zone register and compare this value with vrhot# trip threshold programmed in the svid register 22h. for the adc conversion, v temp =0.9v equates to 64h stored in the register 17h. MP2935 utilize intelli-phase?s tm on-die temperature sensing output to monitor the hottest phase?s junction temperature. simply connects every intelli-phase?s tm vtemp pin to MP2935?s temp. connect a 1k ? resistor from temp pin to ground to sink the voltage when temperature is going down. vr_hot# trip point is programmable by tmax pin. the hysteresis of vr_hot# is around 3% of the maximum temperature stored in the register 22h. the tolerance on vr_hot# should be 4% or approximately 4c at 100c setting. tmax r 250 tmax ?? if the desire tmax is 100 o c, then select 25k ? for r tmax . start up sequence MP2935 must strictly follow the start-up sequence shown in figure 13. figure 13 shows the diagrams of the start-up sequence described below: (1) vcc ramps up to 5v. (2) vr controllers receive hardware enable, i.e. en is high. it takes 35s (t1) from en high to vdd ramped to 3.3v. (3) svid bus exits reset state when the vdd is higher than its uvlo threshold. the part is ready to accept svid command 1.6ms (t2) after vdd reached 3.3v. (4) soft-start begins (dac output starts to ramp up) 1.6ms (t2) after vdd reached 3.3v. vr ramps to the v boot voltage with slow slew rate. once vr reached the v boot voltage, it asserts vr_settle, alert# and vr_rdy. (6) (5) start up sequence finished. notes: 6) cpu determines when the alert# signal is cleared. it may clear alert# after the rail is up.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 37 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. setvid_slow vdd (3.3v) vcc (5v) en vid svid bus vout vr_settle vr_rdy alert# t2 alert# is only cleared after cpu sends the read status command t1 ack getreg status ack pay load t3 figure 13: start-up sequence
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 38 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. svid operation and registers the svid operation and registers follow the vr12/imvp7 svid protocol, rev. 1.5, issued by intel. svid is a three-wire (clock, data and alert) synchronous serial interface that transfers power management information between a master (the cpu) and slaves (MP2935). the clock is source- synchronous from the cpu. the master drives the sclk signal with a low-voltage open drain driver, and may shut down the sclk signal to save power in the absence of data to transfer. sdio is a low-voltage, open-drain data signal that the master and slaves use to send information to each other. the pull-ups for sdio are a nominal 55 ? impedance bus. the reference voltage for sdio and sclk is the processor?s i/o voltage (typically v tt =1.0-1.1v). the bus operates up to a maximum frequency of 26.25mhz. the alert line, alert#, is an active- low signal driven asynchronously from the slave device, prompting the master to read the status register. all signals are routed between the master and the slave or multiple slaves on a common bus?the master cpu and the vr slaves are the only devices allowed on the bus. figure 14 shows the block diagram of the svid controller. figure 14: block diagram of svid controller the vid slew rate control block digitally ramps up/down the 8-bit vids to the final vid codes set by master at a given slew rate. for example, if the vid chip gets a setvid_fast command from the cpu with a new set of vids as the master payload contents, an internal register latches the new vids immediately. meanwhile, an 8-bit counter starts to count up/down from the previous vids to the new codes. the internal clock determines the counting speed: the MP2935 has a 4mhz internal id clock and supports a slew rate of up to 20mv/ s. when MP2935 receives 8-bit vid codes, it automatically converts the vids into an internal reference voltage. the final_vid signal, dvid, indicates that the svid controller will finish vid ramping soon. dvid signal de-asserts once the vid controller gets a new vid command from cpu, then the svid controller ramps up/down the vid code to the target vid step-by-step. dvid signal asserts again when the current
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 39 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. vid code is within 10mv or 1 vid step from the target voltage. dvid is the enable signal of vrsettle comparator. the sensed output voltage is compared to the dac output to determine vrsettle signal when the dvid is asserted. svid address to support multiple MP2935 used on the same svid bus, use the addr pin to program the svid address for each MP2935. there is a 10 a current on the addr pin; connect a resistor from addr pin to ground to set the addr voltage. the internal adc converts the pin voltage to set the svid address. table 6 shows the svid address for different resistor values from addr pin to ground. address 0xe and 0xf are reserved as an ?all call? address used for the cpu to communicate with all slave devices on the bus. table 6: svid address vs addr resistor r addr (k ? ) address (hex) 0 0x0 11.8 0x1 19.6 0x2 28 0x3 35.7 0x4 44.2 0x5 51.1 0x6 59 0x7 68.1 0x8 80.6 0x9 88.7 0xa 95.3 0xb 105 0xc 133 0xd
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 40 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. svid commands table 7: supported svid commands command master payload contents salve payload contents descriptions 01h setvid-fast individual address and all call address vid code n/a set the new vid target. vr transitions to new a vid target at a controlled (up or down) slew rate programmed by the vr. when vr receives a vid moving-up command, it exits all low-powe r states to the normal state to ensure the fastest slew rate to the new vr. 02h setvid-slow individual address and all call address vid code n/a set the vid target. vr transitions to new a vid target at a controlled slew rate (up or down) programmed by the vr. setvid-slow is 4x slower than setvid-fast. when vr receives a vid moving-up command it exits all low power states to the normal state to ensure a slow slew rate to the new vr. 03h setvid-decay individual address and all call address vid code n/a sets the vid target, vr transi tions to new the vid target, but does not control the slew rate; the output voltage decays at a rate proportional to the load current. setvid_decay is only used when vid is falling. vr sets vr_settled bit, but alert line is not 04h setps individual address and all call address byte indicating power status of cpu n/a sends information to vr controller so it can configure vr to improve efficiency, especially at light load 05h setregadr individual address only. nak all call address address of the index in the data table n/a sets the address pointer in the data register table. typically the next command, setregdat, gets loaded into this address. however for multiple writes to the same address, use only one setregadr. 06h setregdat individual address only. nak all call address new data register contents n/a writes the contents to the data register that was previously identified by the address pointer with setregadr. 07h getreg individual address only. nak all call address define which register specified register contents slave returns the contents of t he specified register as the payload. see table 8 for list of registers the majority of the vr monitoring data is accessed through the getreg command.
MP2935 ? 4-phase pwm controller for vr12.5 applications MP2935 rev. 1.02 www.monolithicpower.com 41 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. svid data and config uration registers table 8 shows the supported registers. table 8: svid registers index register name access default value (otp) 00h vendor id r 25h 01h product id r 02h product revision r 03h date code r hard coded 04h lot code r hard coded 05h protocol id r 02h (for vr12.5), hard code registers 00h-06h are programmed by the vr vender at time of manufacture and are read only. this information is used to identify the vender's part in the field or during platform manufacture. 06h capability r d7h 10h status_1 r 00h 11h status_2 r 00h 12h temperature zone r 00h 15h output current (i out ) r actual i out measured after start-up 16h output voltage r 17h vr temperature r registers 10h-18h are read-write telemetry data registers that the pwm controller updates. the master can read these registers, but not write. 18h output power (p out ) r 19h input current r 1ah input voltage r 1bh input power r 1ch status_2_last read r 21h icc_max r 00h 22h temp_max r 96h (150c) 24h sr_fast r 0ah (10mv/ s) 14h (20mv/ s) 25h sr_slow r 05h(5mv/ s) for fast@20mv/ s 02h (2.5mv/ s) for fast@10mv/ s registers 21h-29h are otp or pin- programmed with platform vr design points. if pin-programmed, the vr must load the data registers when its power is applied to the vr control ic. 26h v boot r 7eh (1.75v) 30h v out_max rw ffh (3.04v) 31h vid setting rw 00h 32h pwr state rw 00h 33h offset rw 00h 34h multi vr config rw 00h registers 30h-35h are scratch;pad registers, programmed by the master with setvid_x, setps or setregdat commands. these registers revert to default values when power is removed. 35h setregadr rw
MP2935 ? 4-phase pwm controller for vr12.5 applications notice: the information in this document is subject to change with out notice. please contact mps for current specifications. users should warrant and guarantee that third party intellectual property rights ar e not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP2935 rev. 1.02 www.monolithicpower.com 42 8/25/2015 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2015 mps. all rights reserved. package information 6x6mm qfn40 side view top view 5.90 6.10 5.90 6.10 0.80 1.00 0.00 0.05 0.20 ref pin 1 id marking note: 1) all dimensions are in millimeters . 2) exposed paddle size does not include mold flash . 3) lead coplanarity shall be 0.10 millimeter max. 4) drawing conforms to jedec mo-220, variation vjjd-5. 5) drawing is not to scale. pin 1 id option a 0.30x45 o typ. pin 1 id option b r0.25 typ. detail a pin 1 id index area 1 40 31 30 21 20 11 10 bottom view pin 1 id see detail a 4.50 4.80 4.50 4.80 0.50 bsc 0.35 0.45 0.18 0.30 recommended land pattern 0.70 0.50 0.25 4.70 5.90

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